Wipro Limited is a multinational IT Consulting and System Integration services company headquartered in Bangalore, Karnataka, India.
Wipro Ltd is a global information technology, consulting and outsourcing company with 145,000 employees serving over 900 clients in 60 countries. The company posted revenues of $6.9 billion for the financial year ended Mar 31, 2013.
To focus on core IT Business, it demerged its non-IT businesses into a separate company named Wipro Enterprises Limited with effect from 31 March 2013. The demerged company offers consumer care, lighting, healthcare and infrastructure engineering and contributed to approx. 10% of the revenues of Wipro Limited in previous financial year.
Wipro always looking for Talented, experienced and Desire candidates for work with the Company. we provide betterfacilities for our Employees. If you want to Join please visit company website (http://careers.wipro.com) and submit your Resume.
Detail of Current Jobs Opportunities :
1. Job Position :VLSI Tech Lead – AMS Layout
Job description :
Industry experience in analog/custom digital/Standard cell layout
Worked in layout of any one of the following is required:
Power Management blocks, PLL, PHY, LDO, high performance ADCs, high speed IO’s or Standard cells, integration
Should have minimum of 8 years of experience in analog/mixed signal design
Knowledge of analog circuits like DCDC. Low-drop-out regulators, charge pumps, LNA, RF-PA,SPDT,ADC/DAC, PLL and high speed chip interfaces (HDMI, LVDS, DVI, PCIE, USB), high-speed multi-GB/s SerDes design and clock generation/distribution is required
Good understanding of Fine, Bi-CMOS and BCD process technology is also needed
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 6 to 10 Years
2. Job Position :VLSI Senior Engineer – AMS Layout
Job description :
Industry experience in 20nm/28nm IO cell/standard cell/analog/custom digital/Standard cell layout
Worked in Layout of any one of the following is required : Power Management blocks, PLL, PHY, LDO, high performance ADCs, high speed IO’s or Standard cells, integration and taking the block from specification to release.
Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc.
Qualification :BE/B Tech/MCA/MTech/MSc
Location :Bangalore
Experience :4 to 6 Years
3. Job Position : VLSI Tech Architect/Lead – AMS Design
Job description : Development of Analog/Mixed Signal IP/IC for power management or medical application or communication application or RF application
Knowledge of analog circuits like DCDC. Low-drop-out regulators, charge pumps, LNA, RF-PA,SPDT,ADC/DAC, PLL and high speed chip interfaces (HDMI, LVDS, DVI, PCIE, USB), high-speed multi-GB/s SerDes design and clock generation/distribution is required
Good understanding of Fin Fet, Bi-CMOS and BCD process technology is also needed
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 10 to 13 Years /6 to 10 Years
4. Job Position : AMS-I/O-Design
Job description :
Good expertise in standard cell design and characterization
Experience in 28nm and higher process nodes is a must
Experience in 1x and other 2x (20nm) is a plus
Experience in building, characterization and QA of standard cell libraries from scratch for 1x/2x and higher process nodes of different flavours (G, LP, HS). Should understand the trade-offs of one flavour vs the other
Experience in grooming freshers to do tasks required for characterization and QA of standard cell libraries
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 10 to 13 Years /6 to 10 Years
5. Job Position : AMS-I/O-Layout
Job description :
5 years Industry experience in I/O layout
Good understanding of I/O layout concepts including ESD
Experience in 40nm and 28nm I/O layout
Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc.
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 6 to 10 Years
6. Job Position :VLSI Tech Lead/Engineer – System Design
Job description :
BE in Electrical/Electronics & Communications and/or ME/Mtech
3 to 8 yrs of experience in field of Signal Integrity and design of High Speed PCB’s
Pre-Layout simulation experience using HSPICE or any other Spice tool
Familiarity with Allegro tools or other layout tools, ADS, Ansys tools for Post layout simulation
Familiarity with interfaces like HDMI, MIPI, USB2/3, GPIO’s , Memory – DDR2/DDR3/LPDDR2, eMMC and other I/O’s meant for Smartphone’s
Some experience in Validation of High Speed boards for Signal Integrity
Experience using IBIS model, linear buffer model, IBIS-AMI for Signal Integrity Simulation
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 6 to 10 Years
7. Job Position : VLSI Tech Lead/Engineer – System Design
Job description :
BE in Electrical/Electronics & Communications and/or ME/Mtech
3 to 8 yrs of experience in field of Signal Integrity and design of High Speed PCB’s
Pre-Layout simulation experience using HSPICE or any other Spice tool
Familiarity with Allegro tools or other layout tools, ADS, Ansys tools for Post layout simulation
Familiarity with interfaces like HDMI, MIPI, USB2/3, GPIO’s , Memory – DDR2/DDR3/LPDDR2, eMMC and other I/O’s meant for Smartphone
Some experience in Validation of High Speed boards for Signal Integrity
Experience using IBIS model, linear buffer model, IBIS-AMI for Signal Integrity Simulation
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 4 to 7 Years
8. Job Position :VLSI Tech Lead – Verification
Job description :
Pre-Silicon functional verification Senior Engineer with MS-EE/B-Tech-EE/ECE3
Skill set and experience
At least 3+ years’ experience in pre-silicon verification
Expertise in Building scalable HVL based verification environment from Scratch using System Verilog OVM/UVM
Good experience in System Verilog – OVM/UVM based verification environment development
Understanding PCI-E, USB, SATA, DDR3 type protocols would be a plus
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore/Pune/Kochi
Experience : 6 to 10 Years
9. Job Position : VLSI Senior Engineer – Verification
Job description :
APB/AHB/AXI protocol understanding
Understanding & exposure to SoC verification env and standard peripheral knowledge
BFM/Scoreboard development
VMM/OVM/UVM methodology understanding
Working with Standard tools NCSIM, VCS
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore/Pune/Kochi
Experience : 4 to 7 Years
10. Job Position : VLSI Senior Engineer – Physical Design
Job description :
Experience in Physical Design
Synthesis/STA- Custom layout flow (experience along with PD flow is good)
Handled a complex block implementation or preferably a full chip implementation. Most complex block < 1M gates, handled multiple blocks
Covered most of the flow (floor planning, Place and route, STA, timing closure, Physical verification)
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore/Hyderabad
Experience : 4 to 7 Years
How To Apply : To apply on any of the Above mentioned opportunities, please send across your resume tovlsicareers.pes@wipro.com
For Jobs Detail & APPLY Visit : http://careers.wipro.com/jobs/job3.htm OR http://careers.wipro.com
Wipro Limited is a multinational IT Consulting and System Integration services company headquartered in Bangalore, Karnataka, India.Wipro Ltd is a global information technology, consulting and outsourcing company with 145,000 employees serving over 900 clients in 60 countries. The company posted revenues of $6.9 billion for the financial year ended Mar 31, 2013.
To focus on core IT Business, it demerged its non-IT businesses into a separate company named Wipro Enterprises Limited with effect from 31 March 2013. The demerged company offers consumer care, lighting, healthcare and infrastructure engineering and contributed to approx. 10% of the revenues of Wipro Limited in previous financial year.
Industry experience in analog/custom digital/Standard cell layout
Worked in layout of any one of the following is required:
Power Management blocks, PLL, PHY, LDO, high performance ADCs, high speed IO’s or Standard cells, integration
Should have minimum of 8 years of experience in analog/mixed signal design
Knowledge of analog circuits like DCDC. Low-drop-out regulators, charge pumps, LNA, RF-PA,SPDT,ADC/DAC, PLL and high speed chip interfaces (HDMI, LVDS, DVI, PCIE, USB), high-speed multi-GB/s SerDes design and clock generation/distribution is required
Good understanding of Fine, Bi-CMOS and BCD process technology is also needed
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 6 to 10 Years
Industry experience in 20nm/28nm IO cell/standard cell/analog/custom digital/Standard cell layout
Worked in Layout of any one of the following is required : Power Management blocks, PLL, PHY, LDO, high performance ADCs, high speed IO’s or Standard cells, integration and taking the block from specification to release.
Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc.
Qualification :BE/B Tech/MCA/MTech/MSc
Location :Bangalore
Experience :4 to 6 Years
Knowledge of analog circuits like DCDC. Low-drop-out regulators, charge pumps, LNA, RF-PA,SPDT,ADC/DAC, PLL and high speed chip interfaces (HDMI, LVDS, DVI, PCIE, USB), high-speed multi-GB/s SerDes design and clock generation/distribution is required
Good understanding of Fin Fet, Bi-CMOS and BCD process technology is also needed
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 10 to 13 Years /6 to 10 Years
Good expertise in standard cell design and characterization
Experience in 28nm and higher process nodes is a must
Experience in 1x and other 2x (20nm) is a plus
Experience in building, characterization and QA of standard cell libraries from scratch for 1x/2x and higher process nodes of different flavours (G, LP, HS). Should understand the trade-offs of one flavour vs the other
Experience in grooming freshers to do tasks required for characterization and QA of standard cell libraries
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 10 to 13 Years /6 to 10 Years
5 years Industry experience in I/O layout
Good understanding of I/O layout concepts including ESD
Experience in 40nm and 28nm I/O layout
Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc.
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 6 to 10 Years
BE in Electrical/Electronics & Communications and/or ME/Mtech
3 to 8 yrs of experience in field of Signal Integrity and design of High Speed PCB’s
Pre-Layout simulation experience using HSPICE or any other Spice tool
Familiarity with Allegro tools or other layout tools, ADS, Ansys tools for Post layout simulation
Familiarity with interfaces like HDMI, MIPI, USB2/3, GPIO’s , Memory – DDR2/DDR3/LPDDR2, eMMC and other I/O’s meant for Smartphone’s
Some experience in Validation of High Speed boards for Signal Integrity
Experience using IBIS model, linear buffer model, IBIS-AMI for Signal Integrity Simulation
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 6 to 10 Years
BE in Electrical/Electronics & Communications and/or ME/Mtech
3 to 8 yrs of experience in field of Signal Integrity and design of High Speed PCB’s
Pre-Layout simulation experience using HSPICE or any other Spice tool
Familiarity with Allegro tools or other layout tools, ADS, Ansys tools for Post layout simulation
Familiarity with interfaces like HDMI, MIPI, USB2/3, GPIO’s , Memory – DDR2/DDR3/LPDDR2, eMMC and other I/O’s meant for Smartphone
Some experience in Validation of High Speed boards for Signal Integrity
Experience using IBIS model, linear buffer model, IBIS-AMI for Signal Integrity Simulation
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore
Experience : 4 to 7 Years
Pre-Silicon functional verification Senior Engineer with MS-EE/B-Tech-EE/ECE3
Skill set and experience
At least 3+ years’ experience in pre-silicon verification
Expertise in Building scalable HVL based verification environment from Scratch using System Verilog OVM/UVM
Good experience in System Verilog – OVM/UVM based verification environment development
Understanding PCI-E, USB, SATA, DDR3 type protocols would be a plus
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore/Pune/Kochi
Experience : 6 to 10 Years
Understanding & exposure to SoC verification env and standard peripheral knowledge
BFM/Scoreboard development
VMM/OVM/UVM methodology understanding
Working with Standard tools NCSIM, VCS
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore/Pune/Kochi
Experience : 4 to 7 Years
Experience in Physical Design
Synthesis/STA- Custom layout flow (experience along with PD flow is good)
Handled a complex block implementation or preferably a full chip implementation. Most complex block < 1M gates, handled multiple blocks
Covered most of the flow (floor planning, Place and route, STA, timing closure, Physical verification)
Qualification : BE/B Tech/MCA/MTech/MSc
Location : Bangalore/Hyderabad
Experience : 4 to 7 Years
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